On-chip High-Voltage Generator Design by Toru Tanzawa

Author:Toru Tanzawa
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

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By doing the similar procedure for different number of stages, one can plot the optimum points in a single area – η plane, as shown in Fig. 3.42. The area is normalized by the minimum among the data points. Figure 3.42a, b respectively show the results using SPICE simulation and model calculation. Both plots show that (1) power efficiency is about 20 % when the charge pump is designed so as to have the minimum area, i.e., N = 14, f = 100 M-Hz, and R = 700 ohm, (2) power efficiency improves to about 30 % when the area is allowed to be twice as large as the minimum, i.e., N = 10, f = 25 M-Hz, and R = 2 k-ohm, and (3) power efficiency is saturated at larger area. Discrepancy of the model from the SPICE result was about 40 % in an extreme case where the number of stages was as small as 8, which barely generated 15 V, but was within 20 % in nominal cases where the number of stages is 10 or larger. As a result, it is validated that the model can provide the initial values for the circuit parameters when the design specification is given. Table 3.7 summarizes the methodology.

Fig. 3.42Area vs. power efficiency by SPICE simulation (a) and model calculation (b)

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